ARM NVIC
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Question 1 of 20
1. Question
Acronym for NVIC is ______
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Question 2 of 20
2. Question
How many vectored interrupts are supported in LPC1768?
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Question 3 of 20
3. Question
Select the features of NVIC.
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Question 4 of 20
4. Question
The Cortex-M3 processor uses a re-locatable vector table that contains the address of the function to be executed for a particular interrupt handler.
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Question 5 of 20
5. Question
How many interrupt priority levels are supported in lpc1768?
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Question 6 of 20
6. Question
How many external interrupts do we have in lpc1768?
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Question 7 of 20
7. Question
Which function is used to enable the interrupt in NVIC?
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Question 8 of 20
8. Question
The NVIC supports nesting (stacking) of interrupts, allowing an interrupt to be serviced earlier by exerting higher priority.
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Question 9 of 20
9. Question
For enabling the interrupt which register is used in LPC1768?
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Question 10 of 20
10. Question
How to clear the interrupt flag in LPC1768?
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Question 11 of 20
11. Question
How to configure external interrupt as edge triggered interrupt in LPC1768?
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Question 12 of 20
12. Question
By default all the external interrupts are edge triggered in LPC1768.
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Question 13 of 20
13. Question
External interrupt flags are present in which register?
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Question 14 of 20
14. Question
Which register is used to change edge triggering for external interrupts?
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Question 15 of 20
15. Question
Which function is used to disable interrupts in NVIC?
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Question 16 of 20
16. Question
How many non-maskable interrupts are there in LPC1768?
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Question 17 of 20
17. Question
Total no of bits to represent priority in LPC1768 is ________
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Question 18 of 20
18. Question
In NVIC, tightly coupled interrupt controller provides low interrupt latency.
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Question 19 of 20
19. Question
How many system defined exceptions are there in NVIC?
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Question 20 of 20
20. Question
Which interrupt is having highest priority?
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